Referenced at Geek.com
AMD - Athlon - Thunderbird (Athlon with Performance Enhancing Cache) - Athlon-C
The Thunderbird core Athlon is available in the Socket A form factor with 256K of on-die L2 cache. The L2 cache on the TBird is 16-set associative and uses a 64-bit bus, as compared to the Pentium III's (Coppermine) 256-bit cache bus. The Thunderbird is capable of running in multiprocessor configurations and may eventually uses a 200 or 266MHz system bus, which actually runs at 100MHz*2 or 133MHz*2 for the Athlon-C. The bus speed may eventually be pushed up to 166MHz*2 for use with PC2600 DDR memory.
The Thunderbird kept the standard Athlon name, and debuted on June 5, 2000. It shipped first in speed grades from 650MHz to 1GHz, in increments of 50MHz, much like the original Athlon. The AMD website and news announcements only listed 750-1000MHz speeds, but 650 and 700MHz speeds were available as well. Also, check out the standard, or "classic" Athlon. After 1.5GHz, AMD will shift to the Palomino Athlon core from the Thunderbird core.
| Chip | MHz | Bus Speed | L1 Cache | L2 Cache | Mics | Die Size | Trans | Form Factor | US Price | Volts | Watts | SpecInt SpecFP | Avail | | Thunderbird | 650 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 38 | ? | June 5, 2000 | | | 700 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 40 | ? | June 5, 2000 | | | 750 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 43 | ? | June 5, 2000 | | | 800 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 45 | ? | June 5, 2000 | | | 850 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 47 | ? | June 5, 2000 | | | 900 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 50 | ? | June 5, 2000 | | | 950 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 52 | ? | June 5, 2000 | | | 1000 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 54 | ? | June 5, 2000 | | | 1100 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 60 | ? | Ship to OEM Aug 15, 2000 Systems ship August 28, 2000 | | | 1200 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 66 | ? | Oct 17, 2000 | | | 1300 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | $125 | 1.75 | ? | ? | Mar 22, 2001 | | | 1400 | 200 (100*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | $125 | ? | ? | ? | Jun 6, 2001 | | Athlon-C | 1000 | 266 (133*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 54 | ? | Oct 30, 2000 - announce, Feb avail | | Athlon-C | 1133 | 266 (133*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 63 | ? | Oct 30, 2000 - announce, Feb avail | | Athlon-C | 1200 | 266 (133*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | - | 1.75 | 66 | ? | Oct 30, 2000 - announce, Feb avail | | Athlon-C | 1333 | 266 (133*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | $125 | 1.75 | 73 | ? | Mar 22, 2001 | | Athlon-C | 1400 | 266 (133*2) | 128KB -64K I -64K D | 256K on chip | .18 | 117 | 37 mil (15 mil is L2 cache) | Socket A | $125 | ? | ? | 554 458 | Jun 6, 2001 |
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