| Delaying a digital signal Hi, it's been a while since i posted in here ! But i'm hoping someone can help.
I'm looking for a way to delay a digital signal by less than 1 clock period, as shown in my screenie. I'm aware of shift registers & the like, but they would only delay by 1 clock period, which is not what i require.
Can anyone provide, preferably, a simple solution to this, or give me a link to somewhere that could.
TIA |
|
lutful... of ideasPremium
join:2005-06-16
Ottawa, ON | You could pass the signal through some buffers or even number of inverters. I recall there used to be IC delay lines in the old days.
*** quick Google search shows AD8120 which can delay 3 signals by any amount upto 50ns. |
|
 SparkChaserPremium
join:2000-06-06
Downingtown, PA
kudos:3 | reply to Rebirth
How long is a clock period? As Lutful says, some inverter delays could be enough. |
|
 leiboldPremium,MVM
join:2002-07-09
Sunnyvale, CA
kudos:6
 ·SONIC.NET
| reply to Rebirth
30cm of a plain copper trace on the pcb is about 1ns of delay.
1 TTL buffer or inverter is about 4ns of delay (that is what I often used).
As others have asked already, how much delay do you need ?
--
Got some spare cpu cycles ? Join Team Helix or Team Starfire! |
|
|
|
| reply to Rebirth
@ lutful
Thanks for the AD8120 info, it looks interesting.
@ SparkChaser
The clock period isn't finalised yet.
@ leibold
Thanks for the buffer/inverter info.
After thinking about it some more, i think i may have solved it. I'd be happy to hear your comments etc.
I feed the signals into an R/C low pass filter which lies above the signal bandwith, which is in effect a time delay. This feeds into a Schmitt Trigger, & as the signal rises, & at the threshold point it fires & transfers the signals onwards. I've just simulated it, & it appears to work ! |
|
| I guess that would work as long as you don't need an exact or consistent delay. Most capacitors (i.e. X5R rated) are +/-15% (or worse) and the capacitance varies depending on temperature and age.
/M |
|
| reply to Rebirth
|
|
| reply to Rebirth
@ mackey
I would use a close tolerance cap, such as polystyrene etc, if i built it that way.
Thanks very much for the links, i'm sure there might be something in them i could try.
Regards to everyone who responded, have a nice weekend. |
|
 SmokChsrWho let the magic smoke out?Premium
join:2006-03-17
Saint Augustine, FL | reply to mackey
said by mackey:I guess that would work as long as you don't need an exact or consistent delay. Most capacitors (i.e. X5R rated) are +/-15% (or worse) and the capacitance varies depending on temperature and age.
hehe I just love throwing analog components into a digital circuit. It drives digital designers crazy. 
Back in the 80's I designed one that used a RC circuit to give a 700ms delay in a CMOS circuit. I made 2 and both are still in service today, and still time out correctly. I actually would have expected the electrolytic cap to have shifted more by now, but it's hanging in there. |
|
lutful... of ideasPremium
join:2005-06-16
Ottawa, ON Reviews:
·TekSavvy DSL
| reply to Rebirth
said by Rebirth:After thinking about it some more, i think i may have solved it. I'd be happy to hear your comments etc. You may not be happy to hear my comment. What is the actual "problem" you have apparently solved?
a) Are you trying to delay that digital signal so it is not captured too early by some digital flop in the same clock domain?
b) Or is it a clock and you want it delayed to meet setup times at some other IC?
c) ... some other complex reason
said by Rebirth:I feed the signals into an R/C low pass filter which lies above the signal bandwith, which is in effect a time delay. This feeds into a Schmitt Trigger, & as the signal rises, & at the threshold point it fires & transfers the signals onwards. I've just simulated it, & it appears to work ! Please think about my earlier comments.
a) You could simply have latched the signal on the falling edge of the clock
b) clock buffers exist for this reason
c) ... some other simple solution |
|
leiboldPremium,MVM
join:2002-07-09
Sunnyvale, CA
kudos:6 Reviews:
·SONIC.NET
| reply to SmokChsr
said by SmokChsr: I just love throwing analog components into a digital circuit. It drives digital designers crazy. Only those that never learned electronics properly. They tend to think of digital components as black boxes and are ignorant of their true internal nature which consists of analog components (primarily resistors and transistors).
It also works the other way around. I remember reading a book (don't remember the title) with unusual applications for basic TTL gates and several of the examples were analog circuits (like using a single SN7400 as a 25MHz CB-band voice transmitter).
--
Got some spare cpu cycles ? Join Team Helix or Team Starfire! |
|
lutful... of ideasPremium
join:2005-06-16
Ottawa, ON Reviews:
·TekSavvy DSL
| said by leibold:said by SmokChsr: I just love throwing analog components into a digital circuit. It drives digital designers crazy. Only those that never learned electronics properly. They tend to think of digital components as black boxes and are ignorant of their true internal nature which consists of analog components I am trying to imagine adding 700 ms delay via RC+Schmitt Trigger to even a kHz frequency digital signal.  |
|
leiboldPremium,MVM
join:2002-07-09
Sunnyvale, CA
kudos:6 Reviews:
·SONIC.NET
| said by lutful:I am trying to imagine adding 700 ms delay via RC+Schmitt Trigger to even a kHz frequency digital signal. As I'm sure you are well aware, the delay time has to be less then 1/2 the period of the signal being delayed (otherwise you start to reverse the charge of the capacitor before the schmitt-trigger changed its state). This only covers the ideal case with a symmetrical signal (the situation for the RC-delay is worse if the signal consists of a brief pulse).
Someone determined to make that 700ms delay of a 1kHz signal work with RC+Schmitt-Trigger combination would have to use a lot of those delay circuits in series (each for a very small delay). Definitely not a sensible solution but it would work.
--
Got some spare cpu cycles ? Join Team Helix or Team Starfire! |
|
SmokChsrWho let the magic smoke out?Premium
join:2006-03-17
Saint Augustine, FL | reply to lutful
said by lutful:I am trying to imagine adding 700 ms delay via RC+Schmitt Trigger to even a kHz frequency digital signal.
hehe, This was more of a one shot circuit 0.5Hz would have been too fast. The desired outcome was a hold off from carrier kill, until the signal was given to switch antenna patterns, allowing for a full field collapse prior to switching. While in reality it doesn't take 700ms for that to happen, it just sounded better at 700 ms in the relays. Chunk......Chunk..Chunk.... |
|
lutful... of ideasPremium
join:2005-06-16
Ottawa, ON Reviews:
·TekSavvy DSL
| reply to leibold
said by leibold:said by SmokChsr: I just love throwing analog components into a digital circuit. It drives digital designers crazy. Only those that never learned electronics properly. They tend to think of digital components as black boxes and are ignorant of their true internal nature which consists of analog components (primarily resistors and transistors) Standard digital cells (buffer, inverter, and, nand, nor, flop, latch, memory, etc) are composed mostly of transistors and occasional capacitors. Resistors are present mainly in input/output cells. Digital IC designers still have to run some "analog" simulations with spice models of those cells. 
When OP describes the original problem, I suspect that we will find a simple digital solution (using buffer/inverter or latch) is better instead of external resistor/capacitor. |
|
| reply to Rebirth
@ SmokChsr
"I just love throwing analog components into a digital circuit."
I know what you mean !
Nice to hear that they are "still in service today, and still time out correctly"
@ lutful
I'm happy to hear all comments, for & against etc.
"What is the actual "problem" you have apparently solved?"
Please see my screenie
Yes this - "a) Are you trying to delay that digital signal so it is not captured too early by some digital flop in the same clock domain?"
"When OP describes the original problem, I suspect that we will find a simple digital solution (using buffer/inverter or latch) is better instead of external resistor/capacitor."
Yes simple is best, & all ideas etc will be gratefully received.
@ leibold
I also remember years ago seeing a cmos IC used as a phono preamp in some electronics magazine ! They didn't pretend it was HiFi though, just showing what could be done. |
|
lutful... of ideasPremium
join:2005-06-16
Ottawa, ON Reviews:
·TekSavvy DSL
| said by Rebirth:Yes this - "a) Are you trying to delay that digital signal so it is not captured too early by some digital flop in the same clock domain?"
...
Yes simple is best, & all ideas etc will be gratefully received The ideal solution to your problem is a single negative edge latch. They were created to shift the signal to next rising edge.
You can verify that a Schmitt trigger has more transistors inside than a simple latch. And you have added 2 external resistors and a capacitor.
That would have been OK if this "solution" was equal in performance to a simple latch. Simulate some glitches of varying width in the middle of the clock period and see what happens. |
|
| @ lutful
"The ideal solution to your problem is a single negative edge latch"
Thank, sounds good ! What IC would you recommend, in the CMOS series for eg ? I would appreciate a diagram of your proposed solution, so i have a clearer picture.
TIA |
|
lutful... of ideasPremium
join:2005-06-16
Ottawa, ON Reviews:
·TekSavvy DSL
1 edit | said by Rebirth:What IC would you recommend ... diagram of your proposed solution, so i have a clearer picture. Check carefully output (Q) of a D-flop and a D-latch from the exact same input signal (D) and decide which one will be better for your application.
Notice that I inverted the clock (CLK) which will use that Q output. So any change in D will pass to Q as long as it happens a bit before the falling edge of the clock which will capture it.
Think of the third pulse on D as a glitch ... a latch will pass it through when enable is high (your clock is low) but the flop will block it.
If the second pulse on D actually happens in your design, there is too much delay on that trace (may be huge RC value) and you should fix the root cause or slow down the clock.
I mentioned classic 74573/574 just to illustrate the difference between flops/latches. You have to look up D flops/latches for the CMOS voltage/technology you are using. There are negative edge triggered D-flops and latches with negative enables. They will show a tiny bubble beside the CLK/CP or E pins.
I personally like to use a small PLD/FPGA to replace discrete digital gates/flops/latches when there are a lot of them in a design.
P.S. I will post a new thread about cleaning up and delaying a signal by arbitrary amounts. But that solution is only good for microseconds to many seconds. |
|
| reply to Rebirth
@ lutful
Thanks for the extra info. I'll experiment & post back with my results.
Looking forward to the new thread.
Regards |
|
