Now you can't even rely on the underlying hardware sometimes. With semiconductor feature size shrink making individual features closer and closer together, we are starting to see the ability of one circuit to affect adjacent ones. In this case, rapidly manipulating one DRAM row in quick succession might cause bit flips in adjacent rows. If this adjacent row happens to be something like an Intel architecture descriptor table (GDT, LDT), you might be able to gain access to regions of the address space not otherwise possible, including everything.
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en.wikipedia.org/wiki/Row_hammer»
users.ece.cmu.edu/~yoong ··· ca14.pdf»
googleprojectzero.blogsp ··· ain.htmlFrom the discussions I've seen, ECC RAM mitigates it somewhat, but not completely.